Managing the power consumption of ICs is an increasingly difficult challenge, because each new generation of portable device includes expanded features and demands longer battery lives.

Buck regulators are usually the first choice when you design nonisolated step-down regulators unless the ratio of V IN to V OUT is greater than 10, the input voltage is high, or both. Low duty cycle ...

Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore’s Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around ...

As system-on-chip (SoC) designs grow larger, designers must grapple with serious global timing problems, the effect of wire loading and timing delays and the performance hit associated with supporting ...

Clock gating is an effective method of reducing the dynamic power consumption in synchronous circuits. One of the ways to achieve this is by masking the clock that goes to the idle portion of the ...

Technology developed for driving synchronous FETs in flyback topologies can be directly applied in LLC topologies. This technology offers significant gains in efficiency for applications with low ...

Power supplies that use diodes to rectify an ac voltage to obtain a dc voltage must deal with inherent inefficiencies. A standard diode or ultra-fast diode can have a 1-V forward voltage or higher at ...

There are a number of interesting technologies to keep an eye on in term of how and when they could be adopted for use in SoC design today, some of which include gallium arsenide, GPGPUs, 3D ICs and ...